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Chip Scale Package (CSP) Wire Bonding Capability Study...

Rufino Ringor ST Assembly and Test Services Pte. Ltd. 5 Yishun Street 23 Singapore 768442 Jimmy Castaneda SPT Asia Pte. Ltd. 970 Toa Payoh North #07-25/26 Singapore 318992...

Abstract The emergence of the new advanced package technology chip scale package (CSP) in the semiconductor industry has been increasingly becoming popular. In this study, the focus will be made on the CSP package types using wire bonding interconnect technology, which was performed to determine the degree of limitation and challenges of having a short and low looping profile as dictated by the allowable CSP package thickness. T wo major considerations were studied and investigated, namely the short and low wire looping profile, and capillary design. Introduction Chip Scale Package (CSP) are commonly designed and use d for devices like DRAM, SRAM, flash memories, not so high pin count ASIC, and microprocessors. The main difference of a CSP as compared with other package technology is that the package area is less than 1.20 times the chip area. The unique feature of most CSP is the use of a substrate (interposer, or carrier or substrate carrier, or metal layer) to redistribute the very fine pitch (as small as 75 m) peripheral array pads on the chip to a much larger pitch (1mm, 0.8mm, 0.75mm, and 0.5mm) area array pads on the printed circuit board (PCB). Basically most of the CSP's uses either wire bonding or solder bumped flip-chip technology.1 The CSP is seen as a cross between the BGA and flip chip technology due to current board and assembly limitations in handling ultra-fine pitch array packages. The CSP have an advantages as with the substrate, it is easier...

to test at high speed and burn-in for known good die (KGD), to handle, to assemble, to rework, to standardize, to protect the die, to deal with die shrink and expand, and it is subject to less infrastructure constraints.1 The CSP construction and size makes suitable for high lead count I/O (up to 1200). The present assembly infrastructure (e.g. wire bond equipment, etc...) has matured over the years. Changing from one packaging technology into another means new resources and investment. Given this scenario, the semiconductor assembly houses are pushing the limits of the present equipment's capability to optimize its full utilization for new packaging technology like the CSP wire bonding. For short and low looping profile, wire bonder looping capability have been investi...

Document Keywords

Chip Scale Package (CSP) Wire Bonding Capability Study - Brochure - English PDF 571 KB file products bonding capillaries brochures chip scale package csp wire bonding capability study brochure english

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